The present invention relates to photolithography, and in particular relates to the generation of mask layouts for use with dipole illumination techniques. In addition, the present invention relates to a device manufacturing method using a lithographic apparatus comprising a radiation system for providing a projection beam of radiation; a mask table for holding a mask, serving to pattern the projection beam; a substrate table for holding a substrate; and a projection system for projecting the patterned projection beam onto a target portion of the substrate.
Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask contains a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatusxe2x80x94commonly referred to as a step-and-scan apparatusxe2x80x94each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the xe2x80x9cscanningxe2x80x9d direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally  less than 1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing. Thereafter, the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book xe2x80x9cMicrochip Fabrication: A Practical Guide to Semiconductor Processingxe2x80x9d, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
The lithographic tool may be of a type having two or more substrate tables (and/or two or more mask tables). In such xe2x80x9cmultiple stagexe2x80x9d devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic tools are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithography masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD (critical dimension) of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
Furthermore, the constant improvements in microprocessor speed, memory packing density and low power consumption for micro-electronic components are directly related to the ability of lithography techniques to transfer and form patterns onto the various layers of a semiconductor device. The current state of the art requires patterning of CD""s well below the available light source wavelengths. For instance the current production wavelength of 248 nm is being pushed towards patterning of CD""s smaller than 100 nm. This industry trend will continue and possibly accelerate in the next 5-10 years, as described in the International Technology Roadmap for Semiconductors (ITRS 2000).
Lithographic methods aimed at improving resolution, while retaining acceptable process latitude and robustness are classified as Resolution Enhancement Techniques (RET""s) and comprise a very wide range of applications. Examples include: light source modifications (e.g. Off-Axis Illumination), use of special masks, which exploit light interference phenomena (e.g. Attenuated Phase Shift Masks, Alternating Phase Shift Masks, Chromeless Masks, etc.), and mask layout modifications (e.g. Optical Proximity Corrections).
In an off-axis illumination regimen, as illustrated in FIG. 1, increased focus latitude and image contrast are achieved by capturing at least one of the first orders of the pattern spatial frequencies. As shown in FIG. 1, a typical off-axis illumination system includes in-part a light source 11, a mask 12, a lens 13 and the wafer 14 covered with photoresist. With dipole illumination, the light source is confined to two poles, in order to create the conditions for two-beam imaging with theoretical infinite contrast. FIG. 2 illustrates the basic principles of dipole imaging. As shown, a dipole illumination system includes in-part a dipole aperture 16 (or other dipole generating means, such as a suitable diffractive optical element), a condenser lens 17, a mask 18, a projection lens 19 and the wafer 20. The dipole apertures 16 can be of various shapes and orientations, e.g. horizontal, vertical or at any given angle. Exemplary dipole apertures 16 of various sizes and shapes are shown in FIGS. 3(a)-3(h). A detailed description of the concepts of dipole illumination is set forth in U.S. patent application Ser. No. 09/671,802, filed Sep. 28, 2000, which is hereby incorporated by reference.
When dipole illumination is used, resolution is enhanced only for geometrical patterns with orientations perpendicular to the pole orientation axis. For example, a xe2x80x9chorizontalxe2x80x9d dipole allows the patterning of sub-resolution xe2x80x9cverticalxe2x80x9d lines or spaces; the terms xe2x80x9cverticalxe2x80x9d and xe2x80x9chorizontalxe2x80x9d refer to a set of orthogonal directions in the plane of the geometrical pattern. In a typical dipole application for a layout comprising both horizontal and vertical critical patterns, two exposures are needed with two orthogonal dipole sources, one for each exposure. Therefore, the adoption of dipole illumination for patterning critical layers of generalized electronic design layouts, requires the generation of two mask layouts, where orthogonal features are properly partitioned. However, such partitioning can lead to various problems.
More specifically, in order to accurately reproduce the desired pattern on the wafer, it is necessary to identify and compensate for the xe2x80x9cintersectionxe2x80x9d or xe2x80x9cinterconnectionxe2x80x9d areas (e.g., any area/location where a feature positioned in the vertical direction intersects with a feature positioned in the horizontal direction). For example, if all vertical features of a given layout to be printed are included in a xe2x80x9cvertical maskxe2x80x9d and all horizontal features of the layout to be printed are included in a xe2x80x9chorizontal maskxe2x80x9d, any intersection area between a vertical feature and a horizontal feature is essentially printed twice, which likely results in an undesired deviation from the original design layout.
Accordingly, there exists a need for a method of generating mask layouts for use with dipole illumination techniques that compensates for xe2x80x9cintersectionxe2x80x9d areas between orthogonal features so as to allow accurate reproduction of the desired pattern on the wafer.
In an effort to solve the foregoing needs, it is one object of the present invention to provide a method for generating mask layouts for use with dipole illumination techniques that account for and compensate for xe2x80x9cintersectionxe2x80x9d areas created by features which contact one another.
More specifically, in one exemplary embodiment, the present invention relates to a method of generating complementary mask patterns for use in a multiple-exposure lithographic imaging process comprising the steps of:
(a) identifying horizontal critical features and vertical critical features from a plurality of features forming a layout,
(b) identifying interconnection areas, said interconnection areas comprising areas in which one of said horizontal critical features contacts another feature of said layout, and/or areas in which one of said vertical critical features contacts another feature of said layout,
(c) defining a set of primary parameters on the basis of the proximity of said plurality of features relative to one another,
(d) generating an edge modification plan for each interconnection area based on said primary parameters,
(e) generating a horizontal mask pattern by compiling said horizontal critical features, a first shield plan for said vertical critical features and said interconnection areas containing a horizontal critical feature modified by said edge modification plan, said first shield plan being defined by said primary parameters, and
(f) generating a vertical mask pattern by compiling said vertical critical features, a second shield plan for said horizontal critical features and said interconnection areas containing a vertical critical feature modified by said edge modification plan, said second shield plan being defined by said primary parameters.
Although specific reference may be made in this text to the use of the invention in the manufacture of ICs, it should be explicitly understood that the invention has many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the terms xe2x80x9creticlexe2x80x9d, xe2x80x9cwaferxe2x80x9d or xe2x80x9cdiexe2x80x9d in this text should be considered as being replaced by the more general terms xe2x80x9cmaskxe2x80x9d, xe2x80x9csubstratexe2x80x9d and xe2x80x9ctarget portionxe2x80x9d, respectively.
In the present document, the terms xe2x80x9cradiationxe2x80x9d and xe2x80x9cbeamxe2x80x9d are used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g. with a wavelength of 365, 248, 193, 157 or 126 nm) and EUV (extreme ultra-violet radiation, e.g. having a wavelength in the range 5-20 nm).
The term mask as employed in this text may be broadly interpreted as referring to generic patterning means that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate; the term xe2x80x9clight valvexe2x80x9d can also be used in this context. Besides the classic mask (transmissive or reflective; binary, phase-shifting, hybrid, etc.), examples of other such patterning means include:
a) A programmable mirror array. An example of such a device is a matrix-addressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is that (for example) addressed areas of the reflective surface reflect incident light as diffracted light, whereas unaddressed areas reflect incident light as undiffracted light. Using an appropriate filter, the said undiffracted light can be filtered out of the reflected beam, leaving only the diffracted light behind; in this manner, the beam becomes patterned according to the addressing pattern of the matrix-addressable surface. The required matrix addressing can be performed using suitable electronic means. More information on such mirror arrays can be gleaned, for example, from U.S. Pat. No. 5,296,891 and U.S. Pat. No. 5,523,193, which are incorporated herein by reference.
b) A programmable LCD array. An example of such a construction is given in U.S. Pat. No. 5,229,872, which is incorporated herein by reference.
The method of the present invention provides important advantages over the prior art. For example, the present innovation provides a simple method of generating complementary mask layouts for use with dipole illumination techniques that automatically compensate for xe2x80x9cintersectionxe2x80x9d areas between features so as to allow accurate reproduction of the desired pattern on the wafer. Furthermore, the present invention provides the mask designer an additional means of effecting OPC.
Additional advantages of the present invention will become apparent to those skilled in the art from the following detailed description of exemplary embodiments of the present invention.
The invention itself, together with further objects and advantages, can be better understood by reference to the following detailed description and the accompanying drawings.